1. Field of the Invention
The present invention relates to a frequency synthesizer suited in time division multiplexing system, particularly in a time-division-multiplexed signal demultiplexing system for demultiplexing a multiplex signal, obtained by time division multiplexing of plural digital or analog information signals of mutually different sampling or clock frequencies, into original information signals of the state before multiplexing.
2. Related Art
There is a time-division-multiplexed signal demultiplexing system which is capable of facilitating the write-in and read-out control of a memory unit for varying the frequency of clock signal for demultiplexing the time division multiplexed signal, obtained in the above-mentioned system, into the original signals, and enabling a stable demultiplexing operation against a drift in the clock frequency of the signal caused by temperature or Doppler shift of the satellite prior to multiplexing, a drift in the clock frequency of the time division multiplexed signal and a drift of a clock frequency control circuit in the demultiplexing decoder.
In the above-described time division multiplexed transmission system, if dummy data are generated at an interval of x frames after multiplexing, the real information corresponds to (x-1) frames between said dummy data. Therefore, in the regeneration of the original signals from the time division multiplexed signal, it is necessary to maintain the frequency of the read-out clock signal low than 1/N of the frequency of transmission clock signal after time division multiplexing, in order to extend, in signal read-out, the real information of (x-1) frames to the period of x frames of the time division multiplexed signal.
In the system, the write-in frame and read-out frame of a buffer memory are inspected and the frequency of read-out clock signal is controlled according to the difference there-between.
Upon each detection of a dummy flag bit, the write-in operation is temporarily interrupted for a period of .beta. frames. Then the frequency of read-out clock signal is reduced, and, when the difference between the write-in frame and the read-out frame returns to .beta. frames or larger, the frequency of the read-out clock signal is returned to the original value F.sub.W /N thereby regenerating the original data before the time division multiplexing.
Assuming that the minimum period between dummy data is T.sub.min, there stands a relation x.times.T.sub.min &gt;T wherein T is a frequency control period in which the frequency of the read-out clock signal is controlled. Thus the sift in the clock frequency of the information signal after demultiplexing can be made smaller if the change in the read-out clock frequency during the frequency control is smaller.
In the above mentioned system, the read-out clock signal is generated by a frequency synthesizer. When the frequency of read-out clock signal is reduced as the output signal is the frequency synthesizer upon the dummy data detection, the frequency synthesizer is suitable for obtaining an output signal of which phase is continuous from a state where the phase and frequency of the input signal are retained and of which frequency varies little by little from the frequency of the input signal.
In such case, the quality of the regenerated audio signal is improved when the reading clock signal has continuous phase and shows a slight change in the frequency at a time. It is therefore desirable that the change in the frequency of the reading clock signal is selected small.
It has however been difficult to obtain an output signal having a continuous phase and showing successive slight changes in the order of one-millionth in the frequency with respect to the input frequency, for example with a PLL circuit, because the locking function is not satisfactorily achieved.